1. Field of the Invention
The present invention relates to a semiconductor storage device, and an operating method for the semiconductor storage device. In particular, the invention relates to a semiconductor storage device that executes a refreshing operation, and an operating method for the semiconductor storage device.
2. Description of Related Art
In semiconductor storage devices such as a DRAM and a pseudo SRAM, a capacitor of a memory cell accumulates charges to store data. An amount of the charges accumulated in the capacitor is reduced with time due to a leak current or the like. To prevent a data loss, the DRAM or the pseudo SRAM needs to periodically execute a refreshing operation for reading data and rewriting the data for each memory cell. As an example of a refresh mode, a “self-refresh mode” that an internal circuit automatically executes a refreshing operation in response to an internal clock has been known in the art.
FIG. 1 illustrates a typical self-refresh operation. More specifically, FIG. 1 shows the general configuration of a memory cell array 100, and operational timings in a self-refresh operation. In FIG. 1, plural word lines WL0 to WLn cross plural bit lines BL0 to BLm, and memory cells 110 are arranged at each intersection therebetween. As shown in the timing chart of FIG. 1, the self-refresh operation is executed by driving the plural word lines WL0 to WLn sequentially and repeatedly. The word lines are driven based on a clock signal generated by a predetermined timer circuit, and a period necessary for driving all the plural word lines WL0 to WLn is called a “timer period”. For example, a memory cell 110a connected with a word line WLa is refreshed at every timer period.
A longer timer period leads to reduction in power consumed by the self-refresh operation. However, the too long timer period increases a charge leak amount, resulting in a loss of stored data. Regarding the DRAM or pseudo SRAM, an estimated period for holding data is referred to as “hold characteristic”. This hold characteristic varies depending on a state (active or standby state) of each memory cell array 100. For example, under the active state, the hold characteristic (Disturb Hold) is about 30 ms. Under the standby state, the hold characteristic (Static Hold) is about 150 ms. In an active mode, accesses to the memory cells 110 are made, so a leak current increases as compared to a standby mode. As a result, the hold characteristic of the active mode is deteriorated as compared with that of the standby mode. There has been known a technique of setting a timer period in the standby mode longer than that in the active mode for the purpose of saving power consumption by taking advantage of a difference in hold characteristic.
FIG. 2 is a timing chart of a self-refresh operation of a semiconductor storage device as disclosed in International Patent Application Publication No. WO 02/082454. FIG. 2 shows a chip select signal “/CS”, timer period, a refresh pulse for the word line WLa (see FIG. 1), and a refresh pulse for another word line WLb. The chip select signal “/CS” is a signal for controlling an operational state of the semiconductor storage device. The semiconductor storage device enters in an active mode when the chip select signal “/CS” is at a Low level, while the device enters in a standby mode when the chip selection signal “/CS” is at a High level. In the illustrated example of FIG. 2, the chip select signal “/CS” is shifted from the Low level to the High level at a time t1, and the operational state is accordingly changed from the active mode to the standby mode. A given word line WL is refreshed during a timer period T1 in an active mode, and refreshed during a timer period T2 in a standby mode. The timer period T1 is determined based on the “Disturb Hold”. On the other hand, the timer period T2 is determined based on the “Static Hold”, and is set longer than the timer period T1.
As shown in FIG. 2, a period from the last refreshing time for the word line WLa in the active mode to the time t1 is represented as Da. Further, a period from the last refreshing time for the word line WLb in the active mode to the time t1 is represented as Db. The period Da is set longer than the period Db, and more approximate to the timer period T1. Assuming here that at the time t1, the timer period is set to T2 instantly, the memory cell 110a that is expected to be refreshed just after the time t1 cannot be refreshed for a while after the time t1. In some cases, there is a possibility that data stored in the memory cell 110a be lost.
To prevent such a data loss, according to the self-refresh method disclosed in International Patent Application Publication No. WO 02/082454, the timer period is held T1 during a predetermined period (time t1 to time t2) after the operational state is changed to a standby mode. During the predetermined period, all the plural word lines WL0 to WLn are driven. That is, a period from time t1 to time t2 is equal to the timer period T1. As mentioned above, even after the operational state is changed from the active one to the standby one, a refreshing operation for the word lines is executed under the same conditions as those of the active mode until all the word lines are refreshed. As a result, it is possible to prevent a loss of data stored in a memory cell upon the shift from the active mode to the standby mode. To summary, a reliability of the semiconductor storage device improves. From time t2 onward, the timer period is set to T2 that is longer than T1. Hence, it is possible to avoid excessive self-refreshing operations in the standby mode, and save power consumption.
The technique disclosed in International Patent Application Publication No. WO 02/082454 involves the worst case as shown in FIG. 3. FIG. 3 shows the chip select signal “/CS”, the timer period, and consumption current by the refresh operation. In FIG. 3, the chip select signal “/CS” is intermittently shifted to the Low level at regular intervals of several tens of ms. Accordingly, the semiconductor storage device is intermittently put in an active mode at regular intervals of several tens of ms. Such a standby mode period (several tens of ms) is equivalent to the above “Disturb Hold” and to the timer period T1. Thus, according to the technique disclosed in International Patent Application Publication No. WO 02/082454, after the operational state is changed to a standby mode, this operational state returns to the active mode before the timer period is set to T2. As a result, as shown in FIG. 3, the timer period is held T1 irrespective of the standby mode. Accordingly, the consumption current is the same as that of the active mode.
In this worst case, a period corresponding to the active mode is several ms at the longest. That is, a period where the semiconductor storage device is in an active mode is about 1/10 of a period where the device is in a standby mode. Hence, the power consumption is supposed to reduce. However, as mentioned above, the operational state that is changed to the standby mode returns to the active mode before the timer period is set to T2. Therefore, in the worst case of FIG. 3, an expected effect cannot be obtained. There is an increasing demand to save power consumption during a standby mode especially for a memory used in a cell phone, so its specifications are strictly limited. Therefore, a technique capable of saving power consumption even in the worst case of FIG. 3 is required.